SPI slave control register
TRANS_DONE | The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf. |
INT_RD_BUF_DONE_EN | SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
INT_WR_BUF_DONE_EN | SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
INT_RD_DMA_DONE_EN | SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
INT_WR_DMA_DONE_EN | SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
INT_TRANS_DONE_EN | SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
INT_DMA_SEG_TRANS_EN | SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. |
SEG_MAGIC_ERR_INT_EN | 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state. |
TRANS_CNT | The operations counter in both the master mode and the slave mode. |
TRANS_DONE_AUTO_CLR_EN | SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state. |
MODE | Set SPI work mode. 1: slave mode 0: master mode. |
SOFT_RESET | Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. |